The present invention is related to integrated circuit (IC) devices. More particularly, the present invention relates to capacitors formed within IC devices.
High speed switching in an IC results in high transient currents that cause variations in operating supply voltage. The variations in operating supply voltage, often referred to as ground bounce, result in undesirable circuit operation. To minimize variations and assure proper circuit operation, de-coupling capacitors are used to filter much of the noise that may be present between operating supplies such as power and ground. As switching speeds and associated transient currents have increased, de-coupling capacitors have become indispensable building blocks in electronic design.
Traditionally, discrete de-coupling capacitors have been provided external to the IC on a printed circuit board (PCB). Placing de-coupling capacitors on the PCB requires long wire connections between the IC and the de-coupling capacitor. Resistance from the long wire connections in combination with de-coupling capacitance creates an excessively long RC time constant. The long time constant limits the ability of the de-coupling capacitor to filter high frequency noise. In addition to limiting de-coupling capacitor effectiveness, providing discrete de-coupling capacitors on the PCB involves increased component, assembly, and design costs.
To avoid problems related to providing de-coupling capacitors on the PCB, de-coupling capacitors have been integrally combined with an IC chip carrier. Providing de-coupling capacitors as part of the IC chip carrier allows the de-coupling capacitors to be physically closer to the IC. Reduced wire connection resistance due to closer physical location allows for higher IC switching speeds by reducing the RC time constant. However, due to increasing IC density and speeds, chip carrier de-coupling capacitors cannot sufficiently reduce or isolate noise on IC chips placed in the carrier.
De-coupling capacitor effectiveness can be increased and component and assembly costs reduced by integrating de-coupling capacitors into an IC. Various methods of fabricating de-coupling capacitors as part of an integrated circuit have been proposed. Fabrication of parallel plate capacitors using two or more metal layers of an integrated circuit separated by an intervening insulating layer has been utilized as a de-coupling capacitor. A multi-layer capacitor where one layer is a power layer has also been utilized as a de-coupling capacitor. While these types of structure provides a reasonable capacitor, a significant amount of two or more metal layers is consumed to build the capacitor plates. Further, it is difficult and costly to control the thickness of the separating dielectric layer thickness. Without expending the cost and effort required to tightly control of the separating dielectric layer thickness, reliability and yield are negatively impacted. In addition, design rules and design efforts are complicated as multiple layers of the IC design are impacted.
Alternatively, a de-coupling capacitor can consist of two sets of parallel conducting strips formed from distinct metal layers and separated by an insulating layer. Similar to the above-discussed parallel plate technique this technique consumes considerable area of two or more metal layers to realize a capacitor. Area consumed realizing capacitors could otherwise be used for signal or logic wiring. In addition, this technique impacts multiple layers of the IC and the cost and effort required to control insulating layer thickness must be born.
A large area thin gate oxide capacitor can be used to realize de-coupling capacitance. While this type of de-coupling capacitor is useful, it has a number of drawbacks. First, as thin gate oxide capacitors require a large active area, a large die area is consumed to realize a de-coupling capacitor (as much as 20-50% of die area). Next, these large area capacitors are prone to stress failure, thereby limiting yield and/or reliability. For example, if the oxide layer is not as thick as desired, a stress point may develop and, with time, cause the chip to fail. Alternatively, the chip may fail immediately where the oxide layer has a thin hole or other defect. Finally, large semiconductor resistance may result in considerable RC time constant. Similar to mounting de-coupling capacitors on a PCB, increasing the RC time constant reduces the high frequency response of a realized capacitor. Thus, these de-coupling capacitors are expensive, prone to failure and of limited effectiveness.
Thus, there is a need for a reliable, cost effective, high frequency, and high yield IC capacitor. The present invention addresses this need as well as other needs.
One embodiment relates to an integrated circuit comprising a substrate, a dielectric layer disposed over the substrate, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first line disposed adjacent to a second line with an intervening space between the first and second lines. A dielectric material is disposed in the intervening space between the first and the second lines such that a capacitor is formed. The formed capacitor is connected by coupling the first line to a signal and coupling the record line to a capacitor signal.
Another embodiment relates to a metal layer for an IC. The metal layer comprises: (1) a first conductive line coupled to a signal, and (2) a second conductive line coupled to a capacitor signal. Together the first and second conductive lines form a de-coupling capacitor above the dielectric layer and within the metal layer.
Yet another embodiment relates to a method Of manufacturing an integrated circuit including an internal de-coupling capacitor. The method comprises: (1) providing an electrical device upon a substrate; (2) providing an insulative layer over the electrical device and the substrate; and (3) providing a conductive layer over the insulative layer. The conductive layer includes a first conductive line coupled to the electrical device and a second conductive line coupled to a capacitor signal node. Together the first and second conductive lines form a de-coupling capacitor above the dielectric layer.